Formal Semantics and Proof Techniques for Optimizing VHDL Models

Umamageswaran, Kothanda; Pandey, Sheetanshu L.; Wilsey, Philip A.

ISBN 10: 0792383753 / ISBN 13: 9780792383758

Published by Kluwer Academic Publishers, 1998

About this Item

Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. Num Pages: 158 pages, biography. BIC Classification: UMX; UYD. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 234 x 156 x 12. Weight in Grams: 438. . 1998. Hardback. . . . . Books ship from the US and Ireland.

Seller Inventory # V9780792383758

Bibliographic Details

• Title: Formal Semantics and Proof Techniques for Optimizing VHDL Models
• Publisher: Kluwer Academic Publishers
• Publication Date: 1998
• Language: English
• ISBN 10: 0792383753
• ISBN 13: 9780792383758
• Binding: Hardcover
• Condition: New

About this title

Synopsis

Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. The dynamic semantics is presented as a description of what the simulation of VHDL means. In particular it specifies what values the signals of a VHDL description will take if the description were to be executed. An advantage of the approach is that the semantic model can be used to validate different simulation algorithms. The book also presents an embedding of the dynamic semantics in a proof checker which is then used to prove equivalences of classes of VHDL descriptions.
Formal Semantics and Proof Techniques for Optimizing VHDL Models is written for hardware designers who are interested in the formal semantics of VHDL.