Formal Semantics and Proof Techniques for Optimizing VHDL Models

Kothanda Umamageswaran, Sheetanshu L. Pandey et Philip A. Wilsey

ISBN 10: 0792383753 / ISBN 13: 9780792383758

Published by Springer, 1999

About this Item

Ancien livre de bibliothèque avec équipements. Edition 1999. Ammareal reverse jusqu'à 15% du prix net de cet article à des organisations caritatives. ENGLISH DESCRIPTION Book Condition: Used, Very good. Former library book. Edition 1999. Ammareal gives back up to 15% of this item's net price to charity organizations.

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Bibliographic Details

• Title: Formal Semantics and Proof Techniques for Optimizing VHDL Models
• Publisher: Springer
• Publication Date: 1999
• Language: English
• ISBN 10: 0792383753
• ISBN 13: 9780792383758
• Binding: Hardcover
• Condition: Très bon

About this title

Synopsis

Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. The dynamic semantics is presented as a description of what the simulation of VHDL means. In particular it specifies what values the signals of a VHDL description will take if the description were to be executed. An advantage of the approach is that the semantic model can be used to validate different simulation algorithms. The book also presents an embedding of the dynamic semantics in a proof checker which is then used to prove equivalences of classes of VHDL descriptions.
Formal Semantics and Proof Techniques for Optimizing VHDL Models is written for hardware designers who are interested in the formal semantics of VHDL.