Formal Semantics and Proof Techniques for Optimizing VHDL Models
Language: English
Published by Springer, 2012
- Softcover
- New
Seller: Books Puddle, Woodside, NY, U.S.A.Books Puddle
AbeBooks seller since November 22, 2018
Condition: New
US$ 169.94
Quantity: 4 available
Add to basketItem description from seller
pp. 184.
Seller Inventory # 2658569000
- Title
- Formal Semantics and Proof Techniques for Optimizing VHDL Models
- Author
- Philip A. Wilsey Kothanda Umamageswaran Sheetanshu L. Pandey
- Publisher
- Springer
- Publication year
- 2012
- Condition
- New
- Binding
- Soft cover
- Language
- English
- ISBN 10
- 146137331X
- ISBN 13
- 9781461373315
Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.
"Synopsis" may belong to another edition of this title.
Books Puddle
Woodside, NY, U.S.A.
AbeBooks seller since November 22, 2018
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