Hardware Annealing in Analog VLSI Neurocomputing (The Springer International Series in Engineering and Computer Science, 127)

Lee, Bank W., Sheu, Bing J.

ISBN 10: 1461367808 / ISBN 13: 9781461367802

Published by Springer, 2012

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Bibliographic Details

• Title: Hardware Annealing in Analog VLSI Neurocomputing (The Springer International Series in Engineering and Computer Science, 127)
• Publisher: Springer
• Publication Date: 2012
• Language: English
• ISBN 10: 1461367808
• ISBN 13: 9781461367802
• Binding: Paperback
• Condition: Like New
• Book Type: book

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Synopsis

Rapid advances in neural sciences and VLSI design technologies have provided an excellent means to boost the computational capability and efficiency of data and signal processing tasks by several orders of magnitude. With massively parallel processing capabilities, artificial neural networks can be used to solve many engineering and scientific problems. Due to the optimized data communication structure for artificial intelligence applications, a neurocomputer is considered as the most promising sixth-generation computing machine. Typical applica­ tions of artificial neural networks include associative memory, pattern classification, early vision processing, speech recognition, image data compression, and intelligent robot control. VLSI neural circuits play an important role in exploring and exploiting the rich properties of artificial neural networks by using pro­ grammable synapses and gain-adjustable neurons. Basic building blocks of the analog VLSI neural networks consist of operational amplifiers as electronic neurons and synthesized resistors as electronic synapses. The synapse weight information can be stored in the dynamically refreshed capacitors for medium-term storage or in the floating-gate of an EEPROM cell for long-term storage. The feedback path in the amplifier can continuously change the output neuron operation from the unity-gain configuration to a high-gain configuration. The adjustability of the vol­ tage gain in the output neurons allows the implementation of hardware annealing in analog VLSI neural chips to find optimal solutions very efficiently. Both supervised learning and unsupervised learning can be implemented by using the programmable neural chips.