Hierarchical Modeling for VLSI Circuit Testing

Debashis Bhattacharya (u. a.)

ISBN 10: 1461288193 / ISBN 13: 9781461288190

Published by Springer, 2011

About this Item

Hierarchical Modeling for VLSI Circuit Testing | Debashis Bhattacharya (u. a.) | Taschenbuch | xii | Englisch | 2011 | Springer | EAN 9781461288190 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu.

Seller Inventory # 105629787

Bibliographic Details

• Title: Hierarchical Modeling for VLSI Circuit Testing
• Publisher: Springer
• Publication Date: 2011
• Language: English
• ISBN 10: 1461288193
• ISBN 13: 9781461288190
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 235W x 155H x 10D millimeters 235 millimeters width by 155 millimeters height by 10 millimeters depth
• Weight: 277 grams
• Seller catalogs:
  • Bücher

About this title

Synopsis

Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob­ lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving the foregoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models.