High Performance Domino Logic Circuits in Low Power VLSI Design | A Novel Approach

Suman Nehra (u. a.)

ISBN 10: 3659000302 / ISBN 13: 9783659000300

Published by LAP LAMBERT Academic Publishing, 2012

About this Item

High Performance Domino Logic Circuits in Low Power VLSI Design | A Novel Approach | Suman Nehra (u. a.) | Taschenbuch | 68 S. | Englisch | 2012 | LAP LAMBERT Academic Publishing | EAN 9783659000300 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu.

Seller Inventory # 106485269

Bibliographic Details

• Title: High Performance Domino Logic Circuits in Low Power VLSI Design | A Novel Approach
• Publisher: LAP LAMBERT Academic Publishing
• Publication Date: 2012
• Language: English
• ISBN 10: 3659000302
• ISBN 13: 9783659000300
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 220W x 150H x 5D millimeters 220 millimeters width by 150 millimeters height by 5 millimeters depth
• Weight: 119 grams
• Seller catalogs:
  • Bücher

About this title

Synopsis

The advancement of CMOS technologies paved the road for a growing market of mobile and portable electronic devices. This growth is driven by the continual integration of complex analog and digital building blocks on a single chip, so silicon area and power consumption are the two most valued aspects of the design. Compared to static CMOS logic, dynamic logic offers good performance. Wide fan-in logic such as domino circuits is used in high-performance applications. Dynamic domino logic circuits are widely used in modern digital VLSI circuits. These dynamic circuits are often favored in high performance designs because of the speed advantage offered over static CMOS logic circuits. In this dissertation, 2:1 multiplexer and 1:2 decoder is proposed. The proposed 2:1 multiplexer and 1:2 decoder design based on proposed high performance domino logic circuit are tested in 45nm and 65nm technologies to prove its technology independence. Design is also experimented under various substrate-biasing schemes and then the best substrate biasing technique is implemented. The proposed design is better in terms of power, delay and power delay product in comparison to other biasing conditions.

About the Author

B.E., M.Tech. (VLSI Design). Currently working as an Assistant Professor in Faculty of Engineering and Technology, MITS, Lakshmangarh, Sikar, Rajasthan, India.