High Speed Serdes Devices and Applications

The simplest method of transferring data through the inputs or outputs of a silicon chip is to directly connect each bit of the datapath from one chip to the next chip. Once upon a time this was an acceptable approach. However, one aspect (and perhaps the only aspect) of chip design which has not changed during the career of the authors is Moore’s Law, which has dictated substantial increases in the number of circuits that can be manufactured on a chip. The pin densities of chip packaging technologies have not increased at the same pace as has silicon density, and this has led to a prevalence of High Speed Serdes (HSS) devices as an inherent part of almost any chip design. HSS devices are the dominant form of input/output for many (if not most) high-integration chips, moving serial data between chips at speeds up to 10 Gbps and beyond. Chip designers with a background in digital logic design tend to view HSS devices as simply complex digital input/output cells. This view ignores the complexity associated with serially moving billions of bits of data per second. At these data rates, the assumptions associated with digital signals break down and analog factors demand consideration. The chip designer who oversimplifies the problem does so at his or her own peril.

High Speed Serdes Devices and Applications provides a broad understanding of High Speed Serdes (HSS) device usage. The material focuses on HSS devices, and the consolidation of related topics into a single text. Chip and system designers using HSS devices must have detailed knowledge of both the features and functions of the HSS device, and the applications in which they are used. Also designers must have a working knowledge of related subjects, including: reference clock architectures, signal integrity, power dissipation, and test features and functions. The authors consolidate these topics with a specific focus on HSS devices. This approach provides the chip designer sufficient background information for using HSS devices on their chips.

The chapters can be viewed as four distinct sections. The first section relates to the features, functions, and design of HSS devices. Second are chapters that describe the features and functions of protocol logic used to implement various network protocol interface standards. The third section covers specialized topics related to HSS cores. Finally, characteristics of typical design kit models to facilitate integration within the chip design are discussed.

High Speed Serdes Devices and Applications is a useful resource for chip designers using HSS devices in their chip design.