High-k Dielectrics and Metal Gates for Memory Applications | Investigation of High-k Dielectrics and Metal Gate Electrodes for Floating Gate Non-Volatile Memory Applications

Srikant Jayanti

ISBN 10: 3846588474 / ISBN 13: 9783846588475

Published by LAP LAMBERT Academic Publishing, 2012

About this Item

High-k Dielectrics and Metal Gates for Memory Applications | Investigation of High-k Dielectrics and Metal Gate Electrodes for Floating Gate Non-Volatile Memory Applications | Srikant Jayanti | Taschenbuch | 252 S. | Englisch | 2012 | LAP LAMBERT Academic Publishing | EAN 9783846588475 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu.

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Bibliographic Details

• Title: High-k Dielectrics and Metal Gates for Memory Applications | Investigation of High-k Dielectrics and Metal Gate Electrodes for Floating Gate Non-Volatile Memory Applications
• Publisher: LAP LAMBERT Academic Publishing
• Publication Date: 2012
• Language: English
• ISBN 10: 3846588474
• ISBN 13: 9783846588475
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 220W x 150H x 16D millimeters 220 millimeters width by 150 millimeters height by 16 millimeters depth
• Weight: 393 grams
• Seller catalogs:
  • Bücher

About this title

Synopsis

Due to the increasing demand of non-volatile flash memories in the portable electronics, the device structures need to be scaled down drastically. However, the scalability of traditional floating gate structures beyond 20 nm NAND flash technology node is uncertain. In this regard, the use of metal gates and high-k dielectrics as the gate and interpoly dielectrics respectively, seem to be promising substitutes in order to continue the flash scaling beyond 20nm. Furthermore, research of novel memory structures to overcome the scaling challenges need to be explored. Through this work, the use of high-k dielectrics as IPDs in a memory structure has been studied. For this purpose, IPD process optimization and barrier engineering were explored to determine and improve the memory performance. Specifically, the concept of high-k / low-k barrier engineering was studied in corroboration with simulations. In addition, a novel memory structure comprising a continuous metal floating gate was investigated in combination with high-k blocking oxides. Both electrical and analytical characterization studies were undertaken to gain insight into the behavior of the memory layers in the structure.

About the Author

Srikant Jayanti received his B.Tech degree in Electrical Engineering from Indian Institute of Technology – Madras, Chennai in May 2007. He completed his PhD studies at North Carolina State University, Raleigh in December 2011. He specialized in fabrication and characterization of high-k dielectrics/metal gates for advanced logic/memory devices.