Implementation of a Binary Floating Point Fused Multiply-Add Unit

Abdel Aziz Ibrahim, Walaa; Aly Fahmy, Hossam; Hussien Khalil, Ahmed

ISBN 10: 3846546216 / ISBN 13: 9783846546215

Published by LAP LAMBERT Academic Publishing, 2012

About this Item

Seller Inventory # I-9783846546215

Bibliographic Details

• Title: Implementation of a Binary Floating Point Fused Multiply-Add Unit
• Publisher: LAP LAMBERT Academic Publishing
• Publication Date: 2012
• Language: English
• ISBN 10: 3846546216
• ISBN 13: 9783846546215
• Binding: Soft cover
• Condition: New

About this title

Synopsis

The fused multiply add (FMA) operation is very important in many scientific and engineering applications. It is a key feature of the floating-point unit (FPU), which greatly increases the floating-point performance and accuracy.Many approaches are developed on floating-point fused multiply add unit to decrease its latency.two of these approaches are implemented in the Verilog hardware description language. ModelSim10.0c is a used to compile Verilog codes and to simulate them.

About the Author

Walaa Abdel Aziz,Assistant Lecturer,Faculty of Engineering,Modern Academy for Engineering and Technology,Has awarded M.sc. from Electronics and Electrical Communication Department,Faculty of Engineering, Cairo University,March 2011.