Implementation of a Binary Floating Point Fused Multiply-Add Unit
Walaa Abdel Aziz Ibrahim (u. a.)
ISBN 10: 3846546216 ISBN 13: 9783846546215
Published by LAP LAMBERT Academic Publishing, 2012
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Implementation of a Binary Floating Point Fused Multiply-Add Unit | Walaa Abdel Aziz Ibrahim (u. a.) | Taschenbuch | 104 S. | Englisch | 2012 | LAP LAMBERT Academic Publishing | EAN 9783846546215 | Verantwortliche Person für die EU: OmniScriptum GmbH & Co. KG, Bahnhofstr. 28, 66111 Saarbrücken, info[at]akademikerverlag[dot]de | Anbieter: preigu. Seller Inventory # 106128517
Synopsis:
The fused multiply add (FMA) operation is very important in many scientific and engineering applications. It is a key feature of the floating-point unit (FPU), which greatly increases the floating-point performance and accuracy.Many approaches are developed on floating-point fused multiply add unit to decrease its latency.two of these approaches are implemented in the Verilog hardware description language. ModelSim10.0c is a used to compile Verilog codes and to simulate them.
About the Author: Walaa Abdel Aziz,Assistant Lecturer,Faculty of Engineering,Modern Academy for Engineering and Technology,Has awarded M.sc. from Electronics and Electrical Communication Department,Faculty of Engineering, Cairo University,March 2011.
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Bibliographic Details
Title: Implementation of a Binary Floating Point ...
Publisher: LAP LAMBERT Academic Publishing
Publication Date: 2012
Binding: Taschenbuch
Condition: Neu