Implementation of FFT Processor In Nanometer Technologies : Low Power Design Methodologies of FFT Processor

Language: English

Published by LAP LAMBERT Academic Publishing, 2024

6208224608 / 9786208224608

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Seller: AHA-BUCH GmbH, Einbeck, GermanyAHA-BUCH GmbH

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nach der Bestellung gedruckt Neuware - Printed after ordering - OFDM is mainly used to transmit video and audio signals efficiently with high performance and speed. FFT has various applications in, digital signal processing, and biomedical applications. There is a demand for semiconductor technology in terms of high performance, low area and power consumption. This increasing power is a significant problem in current processing communication technology. Therefore, various low-power FFT processors are designed to maximise the system life and meet consumer demand by extending the battery life at a lower cost. In this thesis, FFT processor is designed by using optimized radix 2 DIT butterfly structure with proposed floating point adders and floating point multipliers. The performance of the proposed binary floating point Vedic multiplier is compared with existing floating point multipliers with different adders. The designed cached FFT processor using radix 26 algorithm with SDF pipeline architecture, compared the performance parameters like area, power and operating frequency with existing pipeline architectures. We demonstrated that our proposed Binary floating point Vedic multiplier in Cached radix 26 SDF FFT achieves better power consumption.

Seller Inventory # 9786208224608

Title
Implementation of FFT Processor In Nanometer Technologies : Low Power Design Methodologies of FFT Processor
Author
P. Ramana Reddy
Publisher
LAP LAMBERT Academic Publishing
Publication year
2024
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
6208224608
ISBN 13
9786208224608
Item weight
233 grams
Dimensions
220x150x9 mm

AHA-BUCH GmbH

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