Implementation and Optimization of the Advanced Encryption Standard Algorithm on an 8-Bit Field Programmable Gate Array Hardware Platform

Ryan J Silva

ISBN 10: 1025128508 / ISBN 13: 9781025128504

Published by Creative Media Partners, LLC Mai 2025, 2025

About this Item

Neuware - The contribution of this research is three-fold. The first is a method of converting the area occupied by a circuit implemented on a Field Programmable Gate Array (FPGA) to an equivalent (memory included) as a measure of total gate count. This allows direct comparison between two FPGA implementations independent of the manufacturer or chip family. The second contribution improves the performance of the Advanced Encryption Standard (AES) on an 8-bit computing platform. This research develops an AES design that occupies less than three quarters of the area reported by the smallest design in current literature as well as significantly increases area efficiency. The third contribution of this research is an examination of how various designs for the critical AES SubBytes and MixColumns transformations interact and affect the overall performance of AES. The transformations responsible for the largest variance in performance are identified and the effect is measured in terms of throughput, area efficiency, and area occupied.

Seller Inventory # 9781025128504

Bibliographic Details

• Title: Implementation and Optimization of the Advanced Encryption Standard Algorithm on an 8-Bit Field Programmable Gate Array Hardware Platform
• Publisher: Creative Media Partners, LLC Mai 2025
• Publication Date: 2025
• Language: English
• ISBN 10: 1025128508
• ISBN 13: 9781025128504
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 234W x 156H x 8D millimeters 234 millimeters width by 156 millimeters height by 8 millimeters depth
• Weight: 218 grams

About this title

Synopsis

The contribution of this research is three-fold. The first is a method of converting the area occupied by a circuit implemented on a Field Programmable Gate Array (FPGA) to an equivalent (memory included) as a measure of total gate count. This allows direct comparison between two FPGA implementations independent of the manufacturer or chip family. The second contribution improves the performance of the Advanced Encryption Standard (AES) on an 8-bit computing platform. This research develops an AES design that occupies less than three quarters of the area reported by the smallest design in current literature as well as significantly increases area efficiency. The third contribution of this research is an examination of how various designs for the critical AES SubBytes and MixColumns transformations interact and affect the overall performance of AES. The transformations responsible for the largest variance in performance are identified and the effect is measured in terms of throughput, area efficiency, and area occupied.

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