An Improved Markov Random Field Design Approach For Digital Circuits | Introducing Fault-Tolerance With Higher Noise-Immunity For The Nano-Circuits As Compared To CMOS And MRF Designs

Jahanzeb Anwer (u. a.)

ISBN 10: 3844332634 / ISBN 13: 9783844332636

Published by LAP LAMBERT Academic Publishing, 2011

About this Item

An Improved Markov Random Field Design Approach For Digital Circuits | Introducing Fault-Tolerance With Higher Noise-Immunity For The Nano-Circuits As Compared To CMOS And MRF Designs | Jahanzeb Anwer (u. a.) | Taschenbuch | 88 S. | Englisch | 2011 | LAP LAMBERT Academic Publishing | EAN 9783844332636 | Verantwortliche Person für die EU: BoD - Books on Demand, In de Tarpen 42, 22848 Norderstedt, info[at]bod[dot]de | Anbieter: preigu.

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Bibliographic Details

• Title: An Improved Markov Random Field Design Approach For Digital Circuits | Introducing Fault-Tolerance With Higher Noise-Immunity For The Nano-Circuits As Compared To CMOS And MRF Designs
• Publisher: LAP LAMBERT Academic Publishing
• Publication Date: 2011
• Language: English
• ISBN 10: 3844332634
• ISBN 13: 9783844332636
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 220W x 150H x 6D millimeters 220 millimeters width by 150 millimeters height by 6 millimeters depth
• Weight: 149 grams
• Seller catalogs:
  • Bücher

About this title

Synopsis

As the MOSFET dimensions scale down to nanoscale level, the reliability of circuits based on these devices decreases. Therefore, a mechanism has to be devised that can make the nanoscale systems perform reliably using unreliable circuit components. The solution is fault-tolerant circuit design. Markov Random Field (MRF) is an effective approach that achieves fault-tolerance in integrated circuit design. The previous research on this technique suffers from limitations at the design, simulation and implementation levels. As improvements, the MRF fault-tolerance rules have been validated for a practical circuit example. The simulation framework is extended from thermal to a combination of thermal and random telegraph signal noise sources to provide a more rigorous noise environment for the simulation of nanoscale circuits. Moreover, an architecture-level improvement has been proposed in the design of previous MRF gates. The re-designed MRF is termed as Improved-MRF. By simulating various test circuits in Cadence, it is found that Improved-MRF circuits are 400 whereas MRF circuits are only 10 times more noise-tolerant than the CMOS alternatives.

About the Author

The authors work under the banner of fault-tolerance research group in Universiti Teknologi PETRONAS (UTP). The group is conducting research on various aspects of fault-tolerant circuit design with the support of UTP and MOSTI (Ministry of Science, Technology and Innovation) Malaysia.