Index Generation Functions

Tsutomu Sasao

ISBN 10: 3031799100 / ISBN 13: 9783031799105

Published by Springer International Publishing, Springer International Publishing Okt 2019, 2019

About this Item

Neuware -Index generation functions are binary-input integer valued functions. They represent functions of content addressable memories (CAMs). Applications include: IP address tables; terminal controllers; URL lists; computer virus scanning circuits; memory patch circuits; list of English words; code converters; and pattern matching circuits. This book shows memory-based realization of index generation functions. It shows: 1. methods to implement index generation functions by look-up table (LUT) cascades and index generation units (IGU), 2. methods to reduce the number of variables using linear transformations, and 3. methods to estimate the sizes of memories, with many illustrations, tables, examples, exercises, and their solutions.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 184 pp. Englisch.

Seller Inventory # 9783031799105

Bibliographic Details

• Title: Index Generation Functions
• Publisher: Springer International Publishing, Springer International Publishing Okt 2019
• Publication Date: 2019
• Language: English
• ISBN 10: 3031799100
• ISBN 13: 9783031799105
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 235W x 191H x 11D millimeters 235 millimeters width by 191 millimeters height by 11 millimeters depth
• Weight: 356 grams

About this title

Synopsis

Index generation functions are binary-input integer valued functions. They represent functions of content addressable memories (CAMs). Applications include: IP address tables; terminal controllers; URL lists; computer virus scanning circuits; memory patch circuits; list of English words; code converters; and pattern matching circuits. This book shows memory-based realization of index generation functions. It shows: 1. methods to implement index generation functions by look-up table (LUT) cascades and index generation units (IGU), 2. methods to reduce the number of variables using linear transformations, and 3. methods to estimate the sizes of memories, with many illustrations, tables, examples, exercises, and their solutions.

About the Author

Tsutomu Sasao received B.E., M.E., and Ph.D. degrees in Electronics Engineering from Osaka University, Osaka Japan, in 1972, 1974, and 1977, respectively. He has held faculty/research positions at Osaka University, Japan; IBM T. J. Watson Research Center, Yorktown Heights, NY; the Naval Postgraduate School, Monterey, CA; and Kyushu Institute of Technology, Iizuka, Japan. Now, he is a Professor of Department of Computer Science, Meiji University, Kawasaki, Japan. His research areas include logic design and switching theory, representations of logic functions, and multiple-valued logic. He has published more than 10 books on logic design including, Logic Synthesis and Optimization (1993), Representation of Discrete Functions (1996), Switching Theory for Logic Synthesis (1999), Logic Synthesis and Verification (2002), Progress in Applications of Boolean Functions (2010), Memory-Based Logic Synthesis (2011), and Applications of Zero-suppressed Decision Diagrams (2015). He has served as Program Chairman for the IEEE International Symposium on Multiple-Valued Logic (ISMVL) many times. Also, he was the Symposium Chairman of the 28th IS-MVL held in Fukuoka, Japan in 1998. He received the NIWA Memorial Award in 1979, Takeda Techno-Entrepreneurship Award in 2001, and Distinctive Contribution Awards from IEEE Computer Society MVL-TC for papers presented at ISMVLs in 1986, 1996, 2003, 2004, 2013, and 2018. He has served an associate editor of the IEEE Transactions on Computers. He is a Life Fellow of the IEEE.