This is a tour through recent and prominent works regarding new DRAM chip designs and technologies, near data processing approaches, new memory channel architectures, techniques to tolerate the overheads of refresh and fault tolerance, security attacks and mitigations, and memory scheduling.
The memory system will soon be a hub for future innovation. While conventional memory systems focused primarily on high density, other memory system metrics like energy, security, and reliability are grabbing modern research headlines. With processor performance stagnating, it is also time to consider new programming models that move some application computations into the memory system. This, in turn, will lead to feature-rich memory systems with new interfaces. The past decade has seen a number of memory system innovations that point to this future where the memory system will be much more than dense rows of unintelligent bits.
Rajeev Balasubramonian is a Professor at the School of Computing, University of Utah. He received his B.Tech. in Computer Science and Engineering from the Indian Institute of Technology, Bombay in 1998. He received his M.S. (2000) and Ph.D. (2003) from the University of Rochester. His primary research interests include memory systems, security, and application-specific architectures. Prof. Balasubramonian is a recipient of an NSF CAREER award, faculty research awards from IBM, Google, HPE, an Intel Outstanding Research Award, and various teaching awards at the University of Utah. He has co-authored papers that have been selected as IEEE Micro Top Picks (2007 and 2010) and that have received three best paper awards.
University of Toronto
Margaret Martonosi is the Hugh Trumbull Adams '35 Professor of Computer Science at Princeton University, where she has been on the faculty since 1994. She is also Director of the Princeton's Keller Center for Innovation in Engineering Education, and an A. D. White Visiting Professor-at-Large at Cornell University. From August 2015 through March, 2017, Martonosi was a Jefferson Science Fellow within the U.S. Department of State.
Martonosi's research interests are in computer architecture and mobile computing. Her work has included the widely-used Wattch power modeling tool and the Princeton ZebraNet mobile sensor network project for the design and real-world deployment of zebra tracking collars in Kenya. Her current research focuses on computer architecture and hardware-software interface issues in both classical and quantum computing systems.
Martonosi is a Fellow of IEEE and ACM. Her papers have received numerous long-term impact awards including: 2015 ISCA Long-Term Influential Paper Award, 2017 ACM SIGMOBILE Test-of-Time Award, 2017 ACM SenSys Test-of-Time Paper award, and the 2018 (Inaugural) HPCA Test-of-Time Paper award. Other notable awards include the 2018 IEEE Computer Society Technical Achievement Award, 2010 Princeton University Graduate Mentoring Award, the 2013 NCWIT Undergraduate Research Mentoring Award, the 2013 Anita Borg Institute Technical Leadership Award, and the 2015 Marie Pistilli Women in EDA Achievement Award. In addition to many archival publications, Martonosi is an inventor on seven granted US patents, and has co-authored two technical reference books on power-aware computer architecture. Martonosi completed her Ph.D. at Stanford University.
