Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, . (Lecture Notes in Computer Science)

ISBN 10: 3540230955 / ISBN 13: 9783540230953

Published by Springer, 2004

About this Item

Gebraucht - Sehr gut Ungelesen, vollständig, sehr guter Zustand, leichte Lagerspuren, als Mängelexemplar gekennzeichnet -This book constitutes the refereed proceedings of the 14th International Workshop on Power and Timing Optimization and Simulation, PATMOS 2004, held in Santorini, Greece in September 2004.The 85 revised papers presented together with abstracts of 6 invited presentations were carefully reviewed and selected from 152 papers submitted. The papers are organized in topical sections on buses and communication, circuits and devices, low power issues, architectures, asynchronous circuits, systems design, interconnect and physical design, security and safety, low-power processing, digital design, and modeling and simulation. 926 pp. Englisch.

Seller Inventory # INF1100133922

Bibliographic Details

• Title: Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, . (Lecture Notes in Computer Science)
• Publisher: Springer
• Publication Date: 2004
• Language: English
• ISBN 10: 3540230955
• ISBN 13: 9783540230953
• Binding: Taschenbuch
• Condition: Sehr gut
• Dimensions: 233W x 157H x 50D millimeters 233 millimeters width by 157 millimeters height by 50 millimeters depth
• Weight: 1360 grams

About this title

Synopsis

WelcometotheproceedingsofPATMOS2004,thefourteenthinaseriesofint- national workshops. PATMOS 2004 was organized by the University of Patras with technical co-sponsorship from the IEEE Circuits and Systems Society. Over the years, the PATMOS meeting has evolved into an important - ropean event, where industry and academia meet to discuss power and timing aspects in modern integrated circuit and system design. PATMOS provides a forum for researchers to discuss and investigate the emerging challenges in - sign methodologies and tools required to develop the upcoming generations of integrated circuits and systems. We realized this vision this year by providing a technical program that contained state-of-the-art technical contributions, a keynote speech, three invited talks and two embedded tutorials. The technical program focused on timing, performance and power consumption, as well as architectural aspects, with particular emphasis on modelling, design, charac- rization, analysis and optimization in the nanometer era. This year a record 152 contributions were received to be considered for p- sible presentation at PATMOS. Despite the choice for an intense three-day m- ting, only 51 lecture papers and 34 poster papers could be accommodated in the single-track technical program. The Technical Program Committee, with the - sistance of additional expert reviewers, selected the 85 papers to be presented at PATMOS and organized them into 13 technical sessions. As was the case with the PATMOS workshops, the review process was anonymous, full papers were required, and several reviews were received per manuscript.