This book provides insight into the use of CAD for layout analysis and optimization of interconnect in high speed, high complexity integrated circuits, which have become the dominating factor in determining system performance in nanometer technologies. The text investigates the effects on system performance and reliability of wire size, spacing, wire length, coupling length, load capacitance, rise time of the inputs, place of overlap, frequency, shields, signal direction and wire width for both the aggressors and the victim wires. The authors present a range of CAD algorithms and techniques for synthesizing and optimizing interconnect.

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Interconnect has become the dominating factor in determining system performance in nanometer technologies. Dedicated to this subject, Interconnect Noise Optimization in Nanometer Technologies provides insight and intuition into layout analysis and optimization for interconnect in high speed, high complexity integrated circuits.

The authors bring together a wealth of information presenting a range of CAD algorithms and techniques for synthesizing and optimizing interconnect. Practical aspects of the algorithms and the models are explained with sufficient details. The book investigates the most effective parameters in layout optimization. Different post-layout optimization techniques with complexity analysis and benchmarks tests are provided. The impact crosstalk noise and coupling on the wire delay is analyzed. Parameters that affect signal integrity are also considered.

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