Layout-Aware Analog Synthesis Methodology | Approaches for Parasitic-Inclusive Symbolic Circuit Representation and Extraction for Synthesis

Raoul Badaoui

ISBN 10: 3844304797 / ISBN 13: 9783844304794

Published by LAP LAMBERT Academic Publishing, 2011

About this Item

Layout-Aware Analog Synthesis Methodology | Approaches for Parasitic-Inclusive Symbolic Circuit Representation and Extraction for Synthesis | Raoul Badaoui | Taschenbuch | 176 S. | Englisch | 2011 | LAP LAMBERT Academic Publishing | EAN 9783844304794 | Verantwortliche Person für die EU: BoD - Books on Demand, In de Tarpen 42, 22848 Norderstedt, info[at]bod[dot]de | Anbieter: preigu.

Seller Inventory # 107054461

Bibliographic Details

• Title: Layout-Aware Analog Synthesis Methodology | Approaches for Parasitic-Inclusive Symbolic Circuit Representation and Extraction for Synthesis
• Publisher: LAP LAMBERT Academic Publishing
• Publication Date: 2011
• Language: English
• ISBN 10: 3844304797
• ISBN 13: 9783844304794
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 220W x 150H x 11D millimeters 220 millimeters width by 150 millimeters height by 11 millimeters depth
• Weight: 280 grams
• Seller catalogs:
  • Bücher

About this title

Synopsis

Layout-induced parasitics have significant effects on the behavior of circuits in general and the performance of high-frequency analog ones in particular. To achieve parasite-inclusive performance-closure, layout-aware circuit synthesis methodologies are beginning to emerge. In layout-in-the-loop synthesis methodologies, performance analysis is based on the generation of a concrete layout for the explored circuit sizes. A parasite-inclusive circuit is extracted from the layout using a standard extractor and is analyzed using a simulator to determine whether the required constraints are met; this is time consuming. Various approaches of estimating parasitics lack the correctness that would only come from examining the layout itself. The proposed approach tries to include the exactness of the layout to be generated without actually generating it. It relies on using pre-generated structures for the specified unsized circuit; these structures are generated pre-synthesis and contain the information that a layout would have provided to a synthesis process if it was to be generated. This information contains extraction specifics for modules, their location and routing characteristics.

About the Author

Raoul Badaoui holds a PhD in computer engineering from the University of Cincinnati and a bachelor of engineering from the American University of Beirut. His research focus was on Analog VLSI Electronic Design Automation. He currently works as a research and development engineering lead for Certify, an FPGA prototyping software at Synopsys.