Layout design and verification of CMOS analog integrated circuit: Based on Virtuoso Mentor and Cal Cadence(Chinese Edition)

YIN FEI FEI . CHEN YUE YING DENG ZHU

ISBN 10: 7121298074 / ISBN 13: 9787121298073

About this Item

Paperback. Pub Date:2016-08-01 Pages:272 Language: Publisher: Chinese Electronic Industry Press book based on the Cadence Virtuoso layout design tools and Mentor Calibre layout verification tool. take a gradual approach. introduced by Cadence and Virtuoso.

Seller Inventory # DN058333

Bibliographic Details

• Title: Layout design and verification of CMOS analog integrated circuit: Based on Virtuoso Mentor and Cal Cadence(Chinese Edition)
• ISBN 10: 7121298074
• ISBN 13: 9787121298073
• Binding: paperback
• Condition: New

About this title

Synopsis

本书依托Cadence Virtuoso版图设计工具与Mentor Calibre版图验证工具，采取循序渐进的方式，介绍利用Cadence Virtuoso与Mentor Calibre进行CMOS模拟集成电路版图设计、验证的基础知识和方法，内容涵盖了CMOS模拟集成电路版图基础知识，Cadence Virtuoso与Mentor Calibre的基本概况、操作界面和使用方法，CMOS模拟集成电路从设计到流片的完整流程，同时又分章介绍了利用Cadence Virtuoso版图设计工具、Mentor Calibre版图验证工具及Synopsys Hspice电路仿真工具进行CMOS电路版图设计与验证、后仿真的实例，包括运算放大器、带隙基准源、低压差线性稳压源、比较器和输入/输出单元。