Logic Optimization and Synthesis Techniques with Area-Power Trade-offs | A Genetic Algorithm based Approach

Sambhu Nath Pradhan

ISBN 10: 3639344723 / ISBN 13: 9783639344721

Published by VDM Verlag Dr. Müller, 2011

About this Item

Logic Optimization and Synthesis Techniques with Area-Power Trade-offs | A Genetic Algorithm based Approach | Sambhu Nath Pradhan | Taschenbuch | Englisch | VDM Verlag Dr. Müller | EAN 9783639344721 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu.

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Bibliographic Details

• Title: Logic Optimization and Synthesis Techniques with Area-Power Trade-offs | A Genetic Algorithm based Approach
• Publisher: VDM Verlag Dr. Müller
• Publication Date: 2011
• Language: English
• ISBN 10: 3639344723
• ISBN 13: 9783639344721
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 150W x 10H x 219D millimeters 150 millimeters width by 10 millimeters height by 219 millimeters depth
• Weight: 317 grams
• Seller catalogs:
  • Bücher

About this title

Synopsis

In recent times, power consumption has been recognized as an important issue in implementing battery-operated portable devices. Power consumption is being addressed in all levels of VLSI design. The saving will be higher if power issues are taken care of early in the design cycle. This has motivated us to consider power issue at the logic level. Due to the exponential nature of leakage in the subthreshold regime operation of transistors, leakage current can no longer be ignored. In this work we have adressed both the dynamic and leakage power consumption of the circuit. The problems addressed in this work handle multiple objectives, such as area, power etc. and a combination of these. Thus, based on relative priority of one over the other, the circuits can be optimized. We have developed both combinational and sequential logic synthesis techniques targeting the trade-offs in the final circuit. Two, and multilevel combinational circuit synthesis and optimization using GA have been presented. Effectiveness of power-gating technique to reduce power dissipation has been examined. A technology specific approach to reduce standby leakage has been developed.

About the Author

Sambhu Nath Pradhan has obtained Ph.D degree from the Dept. of E and ECE, IIT Kharagpur in 2010. Currently he is working as an Assistant Professor in the Dept. of Electronics and Communication Engineering, NIT Agartala. His area of research includes low-power VLSI design and testing.