Logic Synthesis for Finite State Machines Based on Linear Chains of States

Alexander Barkalov

ISBN 10: 3319598368 / ISBN 13: 9783319598369

Published by Springer International Publishing, Springer International Publishing Jul 2017, 2017

About this Item

Neuware -This book discusses Moore finite state machines (FSMs) implemented with field programmable gate arrays (FPGAs) including look-up table (LUT) elements and embedded memory blocks (EMBs). To minimize the number of LUTs in FSM logic circuits, the authors propose replacing a state register with a state counter. They also put forward an approach allowing linear chains of states to be created, which simplifies the system of input memory functions and, therefore, decreases the number of LUTs in the resulting FSM circuit. The authors combine this approach with using EMBs to implement the system of output functions (microoperations). This allows a significant decrease in the number of LUTs, as well as eliminating a lot of interconnections in the FSM logic circuit. As a rule, it also reduces the area occupied by the circuit and diminishes the resulting power dissipation.This book is an interesting and valuable resource for students and postgraduates in the area of computer science, as well as for designers of digital systems that included complex control unitsSpringer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 236 pp. Englisch.

Seller Inventory # 9783319598369

Bibliographic Details

• Title: Logic Synthesis for Finite State Machines Based on Linear Chains of States
• Publisher: Springer International Publishing, Springer International Publishing Jul 2017
• Publication Date: 2017
• Language: English
• ISBN 10: 3319598368
• ISBN 13: 9783319598369
• Binding: Buch
• Condition: Neu
• Dimensions: 241W x 160H x 19D millimeters 241 millimeters width by 160 millimeters height by 19 millimeters depth
• Weight: 524 grams

About this title

Synopsis

This book discusses Moore finite state machines (FSMs) implemented with field programmable gate arrays (FPGAs) including look-up table (LUT) elements and embedded memory blocks (EMBs). To minimize the number of LUTs in FSM logic circuits, the authors propose replacing a state register with a state counter. They also put forward an approach allowing linear chains of states to be created, which simplifies the system of input memory functions and, therefore, decreases the number of LUTs in the resulting FSM circuit. The authors combine this approach with using EMBs to implement the system of output functions (microoperations). This allows a significant decrease in the number of LUTs, as well as eliminating a lot of interconnections in the FSM logic circuit. As a rule, it also reduces the area occupied by the circuit and diminishes the resulting power dissipation.

This book is an interesting and valuable resource for students and postgraduates in the area of computer science, as well as for designers of digital systems that included complex control units