Logical Time @ Work for the Modeling and Analysis of Embedded Systems | Foundations of the UML/MARTE Time Model

Frederic Mallet

ISBN 10: 3843393885 / ISBN 13: 9783843393881

Published by LAP LAMBERT Academic Publishing, 2011

About this Item

Logical Time [at] Work for the Modeling and Analysis of Embedded Systems | Foundations of the UML/MARTE Time Model | Frederic Mallet | Taschenbuch | 124 S. | Englisch | 2011 | LAP LAMBERT Academic Publishing | EAN 9783843393881 | Verantwortliche Person für die EU: BoD - Books on Demand, In de Tarpen 42, 22848 Norderstedt, info[at]bod[dot]de | Anbieter: preigu.

Seller Inventory # 107133376

Bibliographic Details

• Title: Logical Time @ Work for the Modeling and Analysis of Embedded Systems | Foundations of the UML/MARTE Time Model
• Publisher: LAP LAMBERT Academic Publishing
• Publication Date: 2011
• Language: English
• ISBN 10: 3843393885
• ISBN 13: 9783843393881
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 220W x 150H x 8D millimeters 220 millimeters width by 150 millimeters height by 8 millimeters depth
• Weight: 203 grams
• Seller catalogs:
  • Bücher

About this title

Synopsis

Logical time is a relaxed form of time promoted by synchronous languages that is functional, elastic (can be abstracted or refined), and multiform. All these properties make logical time adequate also at design time, whereas precise physical time annotations should only matter in later post-synthesis stages. The Clock Constraint Specification Language (CCSL) is a concrete language dedicated to the modeling and analysis of logical time properties. CCSL was initially defined as a companion for the time model of the UML profile for MARTE. It has now become a full-fledged domain-specific modeling language for capturing causal, chronological and timed relationships. It should complement other syntactic models to capture their underlying model of computation. This book starts by describing the historical models of concurrency that have inspired the construction of CCSL. Then, CCSL is introduced and used to build libraries dedicated to two emerging standard models from the automotive (East-ADL) and the avionic (AADL) domains. Finally, an observer-based technique to verify Esterel and VHDL implementations against CCSL specifications is presented.

About the Author

Dr. Eng. Habil. Frederic Mallet is an Associate Professor in the Computer Science department at Nice-Sophia Antipolis University. He is a member of the AOSTE research unit, a joint team between the I3S Laboratory and INRIA Sophia Antipolis research center. He is a voting member of the OMG revision task forces for MARTE and SysML UML Profiles.