Loop Tiling for Parallelism

Language: English

Published by Springer US Okt 2012, 2012

1461369487 / 9781461369486

Series: Book 132 of 260 - The Springer International Series in Engineering and Computer Science

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Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermanyBuchWeltWeit Ludwig Meier e.K.

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Softcover

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This item is printed on demand - it takes 3-4 days longer - Neuware -Loop tiling, as one of the most important compiler optimizations, is beneficial for both parallel machines and uniprocessors with a memory hierarchy. This book explores the use of loop tiling for reducing communication cost and improving parallelism for distributed memory machines. The author provides mathematical foundations, investigates loop permutability in the framework of nonsingular loop transformations, discusses the necessary machineries required, and presents state-of-the-art results for finding communication- and time-minimal tiling choices. Throughout the book, theorems and algorithms are illustrated with numerous examples and diagrams. The techniques presented in Loop Tiling for Parallelism can be adapted to work for a cluster of workstations, and are also directly applicable to shared-memory machines once the machines are modeled as BSP (Bulk Synchronous Parallel) machines. Features and key topics: Detailed review of the mathematical foundations, including convex polyhedra and cones; Self-contained treatment of nonsingular loop transformations, code generation, and full loop permutability; Tiling loop nests by rectangles and parallelepipeds, including their mathematical definition, dependence analysis, legality test, and code generation; A complete suite of techniques for generating SPMD code for a tiled loop nest; Up-to-date results on tile size and shape selection for reducing communication and improving parallelism; End-of-chapter references for further reading. Researchers and practitioners involved in optimizing compilers and students in advanced computer architecture studies will find this a lucid and well-presented reference work with numerous citations to original sources. 280 pp. Englisch. …

Seller Inventory # 9781461369486

Title
Loop Tiling for Parallelism
Author
Jingling Xue
Publisher
Springer US Okt 2012
Publication year
2012
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
1461369487
ISBN 13
9781461369486
Item weight
429 grams
Dimensions
235x155x16 mm
Series
Book 132 of 260: The Springer International Series in Engineering and Computer Science

BuchWeltWeit Ludwig Meier e.K.

Bergisch Gladbach, Germany

5-star seller

AbeBooks seller since January 11, 2012

Shipping rates from Germany to U.S.A.

Item5 to 15 business days5 to 15 business days
First itemUS$ 25.76US$ 25.76
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BuchWeltWeit Ludwig Meier e.K.

Germany