Low Power and Area Efficient 1024-Point FFT Processors: Using Power Radix with 4-Path Data Processing

Vishnu Vardhan, Dupakuntla/ Balaji, Kunati

ISBN 10: 6200473404 / ISBN 13: 9786200473400

Published by LAP LAMBERT Academic Publishing, 2019

About this Item

68 pages. 8.66x5.91x0.16 inches. In Stock.

Seller Inventory # zk6200473404

Bibliographic Details

• Title: Low Power and Area Efficient 1024-Point FFT Processors: Using Power Radix with 4-Path Data Processing
• Publisher: LAP LAMBERT Academic Publishing
• Publication Date: 2019
• Language: English
• ISBN 10: 6200473404
• ISBN 13: 9786200473400
• Binding: Paperback
• Condition: Brand New
• Weight: 0.15 kilograms

About this title

Synopsis

The Fast Fourier transform (FFT) algorithm with radix-2k is used to accomplish both a radix-2 butterfly and a minimize number with twiddle factor multiplication as Radix-2k delay feedback and radix-K delay commutators are the major well-known pipeline architecture for FFT design. To reduce the memory and area requirement here in this thesis we implemented a novel radix-24 multiple delay commutators called 4-Path Feedforward FFT architecture utilizes the advantage of the radix-2 algorithm. By Combining the advantages of Radix-2 algorithm and feed-forward architecture, the proposed 4-Path radix-24 FFT processor achieves the least hardware requirement of multipliers and power consumption also reduced more when compared with Dual-path Radix-22 delay feedback FFT architecture. The entire FFT algorithms were implemented in Verilog hardware description language and synthesized with Xilinx IЅΕ design suit.