Low Power High Speed Sense Amplifier for CMOS SRAM | Schematic and Analysis

Sakshi Rajput

ISBN 10: 3659242985 / ISBN 13: 9783659242984

Published by LAP Lambert Academic Publishing, 2012

About this Item

Low Power High Speed Sense Amplifier for CMOS SRAM | Schematic and Analysis | Sakshi Rajput | Taschenbuch | Englisch | LAP Lambert Academic Publishing | EAN 9783659242984 | Verantwortliche Person für die EU: LAP Lambert Academic Publishing, Brivibas Gatve 197, 1039 RIGA, LETTLAND, customerservice[at]vdm-vsg[dot]de | Anbieter: preigu.

Seller Inventory # 106288420

Bibliographic Details

• Title: Low Power High Speed Sense Amplifier for CMOS SRAM | Schematic and Analysis
• Publisher: LAP Lambert Academic Publishing
• Publication Date: 2012
• Language: English
• ISBN 10: 3659242985
• ISBN 13: 9783659242984
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 4W x 150H x 220D millimeters 4 millimeters width by 150 millimeters height by 220 millimeters depth
• Weight: 103 grams
• Seller catalogs:
  • Bücher

About this title

Synopsis

One of the major issues in the design of SRAMs is the memory access time (or speed of read operation). For having high performance SRAMs, it is essential to take care of the read speed both in the cell-level design and in the design of a clever sense amplifier. Sense amplifiers are one of the most critical circuits in the organization of CMOS memories. Their performance strongly influences both memory access time and overall memory power consumption. High density memories commonly come with increased bit line parasitic capacitance. These large capacitance slow down voltage sensing and makes bit line voltage swings energy-consuming, which result in slower more power hungry memories. Need for larger memory capacity, higher speed, and lower power dissipation.In this work, design of low power high speed sense amplifier for CMOS SRAMs has been done. It has to sense the lowest possible signal swing from the SRAMs bit lines and its response time should be very fast while keeping the power consumption within a tolerable limit. This sense amplifier will be based on latest architectures available in literature and my focus will be to improve the power consumption and response time.

About the Author

Ms.Sakshi Rajput is working as Assistant Professor in Maharaja SurajmalInstitute of Technology,Delhi.She received B.E.(Hons) in Electronicsand Communication from University of Rajasthan,Jaipur and M.Tech(Hons) in VLSI Design from Guru Gobind Singh Indraprastha University,Delhi .Her research interest includes Low power VLSI design.