Low Power Modem Design | A guidance to use novel algorithms (QPSK) and digital filters (FIR, IIR) with MATLAB, SIMULINK with VHDL and Xilinx FPGA

Georgios Giannakopoulos

ISBN 10: 3659750255 / ISBN 13: 9783659750250

Published by LAP LAMBERT Academic Publishing, 2015

About this Item

Low Power Modem Design | A guidance to use novel algorithms (QPSK) and digital filters (FIR, IIR) with MATLAB, SIMULINK with VHDL and Xilinx FPGA | Georgios Giannakopoulos | Taschenbuch | 172 S. | Englisch | 2015 | LAP LAMBERT Academic Publishing | EAN 9783659750250 | Verantwortliche Person für die EU: OmniScriptum GmbH & Co. KG, Bahnhofstr. 28, 66111 Saarbrücken, info[at]akademikerverlag[dot]de | Anbieter: preigu.

Seller Inventory # 104403943

Bibliographic Details

• Title: Low Power Modem Design | A guidance to use novel algorithms (QPSK) and digital filters (FIR, IIR) with MATLAB, SIMULINK with VHDL and Xilinx FPGA
• Publisher: LAP LAMBERT Academic Publishing
• Publication Date: 2015
• Language: English
• ISBN 10: 3659750255
• ISBN 13: 9783659750250
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 220W x 150H x 11D millimeters 220 millimeters width by 150 millimeters height by 11 millimeters depth
• Weight: 274 grams
• Seller catalogs:
  • Bücher

About this title

Synopsis

This book is mainly concerned on use novel algorithms to reduce the power consumption used in modern digital modems e.g. QPSK. The designing and the simulation it will be in MATLAB. It will involve hardware implementation using VHDL and Xilinx FPGAs. In this project a novel low power modem will be designed for use in communication systems. For the designing it will use some of the modern radio communication technologies such as QPSK (OQPSK, BPSK etc) with the aim of designing and simulate a filter in MATLAB using Gaussian, Rayleigh and Rician channels. The simulation of QPSK and FIR filter will made in the SIMULINK of MATLAB. In this model will generate noise and how may bits it will transmitted and how many errors it will received. The final output of all is that in this model in a screen which called Error Rate Calculation. For the VHDL and Xilinx FPGAs will present an overview of the digital design and VHDL, the logic gates, the ASIC design and FPGAs. Finally for the VHDL and ASIC design, it is present schematic diagrams like full adders, parallel adders and multipliers from the Engineering Capture System (ECS).