Synopsis
Low substrate/lattice temperature (< 300 K) operation of n-MOSFET has been effectively studied by device research and integration professionals in CMOS logic and analog products from the early 1970s. The author of this book previously composed an e-book in this area where he and his co-authors performed original simulation and modeling work on MOSFET threshold voltage and demonstrated that through efficient manipulation of threshold voltage values at lower substrate temperatures, superior degrees of reduction of subthreshold and off-state leakage current can be implemented in high-density logic and microprocessor chips fabricated in a silicon die. In this book, the author explores other device parameters such as channel inversion carrier mobility and its characteristic evolution as temperature on the die varies from 100-300 K. Channel mobility affects both on-state drain current and subthreshold drain current and both drain current behaviors at lower temperatures have been modeled accurately and simulated for a 1 ??m channel length n-MOSFET. In addition, subthreshold slope which is an indicator of how speedily the device drain current can be switched between near off current and maximum drain current is an important device attribute to model at lower operating substrate temperatures. This book is the first to illustrate the fact that a single subthreshold slope value which is generally reported in textbook plots and research articles, is erroneous and at lower gate voltage below inversion, subthreshold slope value exhibits a variation tendency on applied gate voltage below threshold, i.e., varying depletion layer and vertical field induced surface band bending variations at the MOSFET channel surface. The author also will critically review the state-of-the art effectiveness of certain device architectures presently prevalent in the semiconductor industry below 45 nm node from the perspectives of device physical analysis at lower substrate temperature operating conditions. The book concludes with an emphasis on modeling simulations, inviting the device professionals to meet the performance bottlenecks emanating from inceptives present at these lower temperatures of operation of today's 10 nm device architectures.
About the Author
Dr. Nabil Shovon Ashraf was born in Dhaka, Bangladesh in 1974. Currently, Dr. Ashraf serves as an Associate Professor in the Department of Electrical and Computer Engineering of North South University, Dhaka, Bangladesh where he had previously served as an Assistant Professor from September 2014-June 2018. He obtained a Bachelor of Technology degree in Electrical Engineering from Indian Institute of Technology Kanpur, India in 1997. He obtained a Master of Science degree in Electrical Engineering from University of Central Florida, Orlando, USA in 1999. In 2011, he obtained his Ph.D. in Electrical Engineering from Arizona State University, Tempe, USA. From December 2011-May 2014, he wasa Post Doctoral Researcher in the department of Electrical Engineering of Arizona State University Tempe. He was employed as design engineer in RF Monolithics Inc., a surface acoustic wave-based filter design company in Dallas, Texas, USA from August 1999-March 2001. From October 2003–June 2006, he served on the faculty as Assistant Professor of the Department of Electrical and Electronic Engineering at the Islamic University of Technology, Gazipur, Bangladesh. To date Dr. Ashraf has published 6 peer-reviewed journal articles (two IEEE EDS) and 15 international conference proceedings (3 IEEE EDS). In 2016, he published New Prospects of Integrating Low Substrate Temperatures with Scaling-Sustained Device Architectural Innovation with Morgan & Claypool and contributed to two book chapters on interface trap-induced threshold voltage fluctuations in the presence of random channel dopants of scaled n-MOSFET at the invitations of highly accomplished international book editors.
"About this title" may belong to another edition of this title.
