A Management Paradigm for FPGA Design Flow Acceleration

Advances in FPGA density and complexity have not been matched by a corresponding improvement in the performance of the implementation tools. Knowledge of incremental changes in a design can lead to fast turnaround times for implementing even large designs. A high-level overview of an incremental productivity flow, focusing on the back-end FPGA design is provided in this book. This book presents a management paradigm that is used to capture the design specific information in a format that is reusable across the entire design process. A C++ based internal data structure stores all the information, whereas XML is used to provide an external view of the design data. This work provides a vendor independent, universal format for representing the logical and physical information associated with FPGA designs.

Abhay Tavaragiri received his B.E degree in Electronics and Communication from the Delhi College of Engineering in 2007 and his Master's degree in Computer Engineering from Virginia Tech in 2011. He is currently working as a design engineer at Intel Corporation,Hillsboro. His interests include FPGA/ASIC design and design automation.