Explore how a massively parallel SIMD computer tests and compares different arithmetic systems.
This paper presents a software-based computer arithmetic laboratory built on the MasPar MP-1 system. It explains why a 64x64, toroidally connected array of 4-bit processors is a good fit for simulating hardware arithmetic components and for running parallel versions of standard and experimental data types. The work shows how timing and accuracy can be compared across formats such as fixed-point fractions, level-index arithmetic, and residual number systems, using a practical, testable environment.
- Learn how the MP-1’s language MPL and MPFortran support parallel, array-centered programming and subroutines in multiple languages.
- See how fixed-point fractions are implemented with nibble-based representations and how division, overflow and reciprocation are handled.
- Understand how RNS, LI, and SLI arithmetic are modeled and tested on a real parallel platform.
- Discover how the laboratory aims to map algorithms to hardware concepts and to lay a basis for future VLSI and hardware experimentation.
Ideal for readers interested in computer arithmetic, parallel processing, and hardware-software co-design.