The Maspar Mp-1 as a Computer Arithmetic Laboratory (Classic Reprint)

This book explores the use of massively parallel SIMD computer architecture for simulating various forms of computer arithmetic. The author uses a DEC/MasPar MP-1 system with 4096 processors in a square array, to demonstrate the advantages of this architecture for such simulations. The book begins with an introduction to the MasPar architecture and its features. It then summarizes some of the number representations and their corresponding arithmetic data types which have been (or, in some cases, are being) created in this laboratory. In Section 4, the author focuses on the implementation of the symmetric level-index, SLI, arithmetic and uses some of the other arithmetic systems (such as fixed-point fractional arithmetic of various wordlengths) for its internal processing. A modified algorithm for SLI arithmetic is also detailed, which is better suited to a massively parallel implementation and to an eventual VLSI hardware implementation of SLI arithmetic. Through this work, the author seeks to create a "computer arithmetic laboratory" where various arithmetic schemes and algorithms can be simulated and tested. This book will appeal to readers interested in computer architecture, computer arithmetic, and parallel computing.