Memory Controllers for Real-Time Embedded Systems

Verification of real-time requirements in systems-on-chip becomes more complex as more applications are integrated. Predictable and composable systems can manage the increasing complexity using formal verification and simulation. This book explains the concepts of predictability and composability and shows how to apply them to the design and analysis of a memory controller, which is a key component in any real-time system.

Verification of real-time requirements in systems-on-chip becomes more complex as more applications are integrated. Predictable and composable systems can manage the increasing complexity using formal verification and simulation. This book explains the concepts of predictability and composability and shows how to apply them to the design and analysis of a memory controller, which is a key component in any real-time system.

This book is generally intended for readers interested in Systems-on-Chips with
real-time applications. It is especially well-suited for readers looking to use SDRAM memories in systems with hard or firm real-time requirements. There is a strong focus on real-time concepts, such as predictability and composability, as well as a brief discussion about memory controller architectures for high-performance computing.

Readers will learn step-by-step how to go from an unpredictable SDRAM memory,
offering highly variable bandwidth and latency, to a predictable and composable
shared memory, providing guaranteed bandwidth and latency to isolated applications.
This journey covers concepts for making memories and arbiters behave in a
predictable and composable manner, as well as architecture descriptions of hardware
blocks that implement the concepts.

• Provides an overview of trends in embedded system design that make design of real-time SoCs difficult, error-prone, and expensive;
• Introduces the concept of predictability, which is required for formal verification of real-time systems;
• Introduces the concept of composability, which is a divide and conquer technique that enables performance verification per application, instead of monolithic verification for all applications together;
• Describes a novel approach to composability, which applies to any predictable shared resource, thus widely extending the scope of composable platforms. This is the first approachthat can efficiently support SDRAM, which is an essential system component;
• Provides an overview of the SDRAM architecture at a level that is relevant for system designers, not memory designers, and explains why SDRAM architectures are difficult to use in real-time systems;
• Describes concepts, architectures, implementation and worst-case performance analysis of predictable SDRAM accesses, as well as predictable and composable memory arbitration, which can be applied to all memory types