Modeling Microprocessor Performance

Geuskens, Bibiche; Rose, Kenneth

ISBN 10: 0792382145 / ISBN 13: 9780792382140

Published by Kluwer Academic Publishers, 1998

About this Item

Focuses on the development of a design and evaluation tool, named RIPE (Rensselaer Interconnect Performance Estimator). This book contains a discussion of the various models and the underlying assumptions based on actual design practices. Num Pages: 195 pages, biography. BIC Classification: TJFC; UYD. Category: (P) Professional & Vocational. Dimension: 234 x 156 x 14. Weight in Grams: 482. . 1998. Hardback. . . . .

Seller Inventory # V9780792382140

Bibliographic Details

• Title: Modeling Microprocessor Performance
• Publisher: Kluwer Academic Publishers
• Publication Date: 1998
• Language: English
• ISBN 10: 0792382145
• ISBN 13: 9780792382140
• Binding: Hardcover
• Condition: New

About this title

Synopsis

Modeling Microprocessor Performance focuses on the development of a design and evaluation tool, named RIPE (Rensselaer Interconnect Performance Estimator). This tool analyzes the impact on wireability, clock frequency, power dissipation, and the reliability of single chip CMOS microprocessors as a function of interconnect, device, circuit, design and architectural parameters. It can accurately predict the overall performance of existing microprocessor systems. For the three major microprocessor architectures, DEC, PowerPC and Intel, the results have shown agreement within 10% on key parameters.
The models cover a broad range of issues that relate to the implementation and performance of single chip CMOS microprocessors. The book contains a detailed discussion of the various models and the underlying assumptions based on actual design practices. As such, RIPE and its models provide an insightful tool into single chip microprocessor design and its performance aspects. At the same time, it provides design and process engineers with the capability to model, evaluate, compare and optimize single chip microprocessor systems using advanced technology and design techniques at an early design stage without costly and time consuming implementation.
RIPE and its models demonstrate the factors which must be considered when estimating tradeoffs in device and interconnect technology and architecture design on microprocessor performance.