Networks on Chip

As the number of processor cores and IP blocks integrated on a single chip is steadily growing, a systematic approach to design the communication infrastructure becomes necessary. Different variants of packed switched on-chip networks have been proposed by several groups during the past two years. This book summarizes the state of the art of these efforts and discusses the major issues from the physical integration to architecture to operating systems and application interfaces. It also provides a guideline and vision about the direction this field is moving to. Moreover, the book outlines the consequences of adopting design platforms based on packet switched network. The consequences may in fact be far reaching because many of the topics of distributed systems, distributed real-time systems, fault tolerant systems, parallel computer architecture, parallel programming as well as traditional system-on-chip issues will appear relevant but within the constraints of a single chip VLSI implementation.

From the reviews:

"This edited book is concerned with the fundamentals of Networks-on-Chip design. ... Overall, the various authors have done an excellent job in covering their material, and the book is well edited. The authors’ objectives were that of providing an in-depth, up-to-date, unified and comprehensive treatment ... . These are difficult objectives ... and they have done a creditable job of attaining them. In summary, this book is a welcome addition to the literature on networks on chip design ... ." (Mile Stojcev, Microelectronics Reliability, Vol. 44, 2004)