Next-Generation Floating-Point Arithmetic Unit

A Arunkumar Gudivada

ISBN 10: 6208117259 / ISBN 13: 9786208117252

Published by LAP LAMBERT Academic Publishing Sep 2024, 2024

About this Item

This item is printed on demand - Print on Demand Titel. Neuware -The Next-Generation Floating-Point Arithmetic Unit Using QCA for Low-Power Applications explores the use of Quantum-dot Cellular Automata for implementing a Floating-Point Arithmetic Unit at the Nano-scale, overcoming limitations of CMOS technology. The research involves designing efficient QCA-based 1-bit and 8-bit full adders, multipliers, and a novel Tree-Based Stack-Type comparator. The proposed FPAU is tested through the implementation of a Fast Fourier Transform algorithm, demonstrating significant improvements in area, power dissipation, and delay compared to existing CMOS-based architectures.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 144 pp. Englisch.

Seller Inventory # 9786208117252

Bibliographic Details

• Title: Next-Generation Floating-Point Arithmetic Unit
• Publisher: LAP LAMBERT Academic Publishing Sep 2024
• Publication Date: 2024
• Language: English
• ISBN 10: 6208117259
• ISBN 13: 9786208117252
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 220W x 150H x 9D millimeters 220 millimeters width by 150 millimeters height by 9 millimeters depth
• Weight: 233 grams

About this title

Synopsis

The Next-Generation Floating-Point Arithmetic Unit Using QCA for Low-Power Applications explores the use of Quantum-dot Cellular Automata for implementing a Floating-Point Arithmetic Unit at the Nano-scale, overcoming limitations of CMOS technology. The research involves designing efficient QCA-based 1-bit and 8-bit full adders, multipliers, and a novel Tree-Based Stack-Type comparator. The proposed FPAU is tested through the implementation of a Fast Fourier Transform algorithm, demonstrating significant improvements in area, power dissipation, and delay compared to existing CMOS-based architectures.