Novel Design of Power and Area Optimization in Sequential circuit

S, Rekha; K R, Nataraj

ISBN 10: 6206719391 / ISBN 13: 9786206719397

Published by LAP Lambert Academic Publishing, 2026

About this Item

Seller Inventory # I-9786206719397

Bibliographic Details

• Title: Novel Design of Power and Area Optimization in Sequential circuit
• Publisher: LAP Lambert Academic Publishing
• Publication Date: 2026
• Language: English
• ISBN 10: 6206719391
• ISBN 13: 9786206719397
• Binding: Soft cover
• Condition: New

About this title

Synopsis

Due to low power dissipation, simple implementation, and high efficiency, complementary metal-oxide semiconductor (CMOS) logic has become the preferred technology for digital VLSI design. Unlike earlier logic families that suffered from continuous bias currents and leakage issues, CMOS offered a major improvement. With VLSI scaling, features such as higher speed, lower power, better reliability, and smaller area have driven major changes in fabrication trends. The emergence of logic styles such as pseudo-NMOS, DCVSL, PTL, and DPTL further reshaped the industry. As performance demands increased, speed and area became dominant design constraints, leading to the development of dynamic and Domino logic families.In any digital circuit, the key design factors are power, speed, area, noise immunity, and cost, which often require careful trade-offs. While Domino logic is widely adopted due to its high speed and compact area, it suffers from high power consumption and noise sensitivity. To overcome these limitations, improved design techniques are required.