On-Chip Time-Domain Metrology in Submicron CMOS

As the complexity and operational speed of today's Systems-on-Chip increase, measuring and characterizing SoC’s building blocks are becoming more challenging. Embedded measuring techniques for system characterization, such as built-in self-test, are therefore becoming necessities. A Time-to-Digital Converter (TDC) is a device that has been widely used to measure the time intervals between two signal edges. The measurement resolution of a simple TDC architecture is limited by the minimum gate delay in the IC fabrication process. When the required time measurement resolution is smaller than the minimum gate delay, many TDC architectures include Time Difference Amplifiers (TDA) to pre-amplify the very short input time intervals. However, the gain of the TDA is usually sensitive to process, voltage, and temperature variations. This work researches techniques on improving measurement characteristic of TDCs and demonstrates a single-stage Vernier TDC with a constant gain TDA. The final designed TDC architecture achieves a linear measurement with a 2.5ps time resolution.

Chin-Hsin Eddy Lin received the B.A.Sc degree in electrical engineering from the University of British Columbia, Vancouver, Canada in 2008 and the M.A.Sc. degree in electrical engineering from Simon Fraser University, Burnaby, Canada in 2012. He is currently a system validation design engineer at PMC-Sierra.