Optimization of area and power of 3D integrated circuits : Optimization of Area and Power of Three-Dimensional Integrated Circuits (3D ICs)

Language: English

Published by LAP LAMBERT Academic Publishing, 2019

6200458960 / 9786200458964

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Seller: AHA-BUCH GmbH, Einbeck, GermanyAHA-BUCH GmbH

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nach der Bestellung gedruckt Neuware - Printed after ordering - Three-dimensional (3D) Integrated Circuits (ICs) has emerged as a new technology providing noticeable solutions to alleviate problems like greater power consumption, longer interconnects with large delays, etc. In 3D ICs, have multiple layers stacked one above the other. Vertical integration of multiple layers scales up the performance of electronic devices beyond Moore's law. It drastically decreases the interconnect length which directly results in increased speed and also combines various technologies (digital, analog, memory, etc.) in a single product, thereby greatly extending the capabilities of System-on-Chip. The objective of this book is to investigate the effects of core utilization on the core and chip area for obtaining the optimal sets of core utilization so that the core and chip area of the 3D ICs can be reduced. Cadence Encounter-to-GDSII has been used for optimization while performing physical designing of the 3D ICs. The literature survey has revealed that majority of the optimization has been performed only at any one of the stages of physical designing while in this book we have done research optimization at three different stages of physical designing.

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Title
Optimization of area and power of 3D integrated circuits : Optimization of Area and Power of Three-Dimensional Integrated Circuits (3D ICs)
Author
Roop Lal
Publisher
LAP LAMBERT Academic Publishing
Publication year
2019
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
6200458960
ISBN 13
9786200458964
Item weight
167 grams
Dimensions
220x150x7 mm

AHA-BUCH GmbH

Einbeck, Germany

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