Output-Capacitor-Free Low-Dropout Regulators: Analysis and Design | Analysis and Design of High-Performance CMOS Output-Capacitor-Free Low-Dropout Regulators for System-on-Chip

Chenchang Zhan (u. a.)

ISBN 10: 3659291889 / ISBN 13: 9783659291883

Published by LAP LAMBERT Academic Publishing, 2012

About this Item

Output-Capacitor-Free Low-Dropout Regulators: Analysis and Design | Analysis and Design of High-Performance CMOS Output-Capacitor-Free Low-Dropout Regulators for System-on-Chip | Chenchang Zhan (u. a.) | Taschenbuch | 144 S. | Englisch | 2012 | LAP LAMBERT Academic Publishing | EAN 9783659291883 | Verantwortliche Person für die EU: OmniScriptum GmbH & Co. KG, Bahnhofstr. 28, 66111 Saarbrücken, info[at]akademikerverlag[dot]de | Anbieter: preigu.

Seller Inventory # 106142894

Bibliographic Details

• Title: Output-Capacitor-Free Low-Dropout Regulators: Analysis and Design | Analysis and Design of High-Performance CMOS Output-Capacitor-Free Low-Dropout Regulators for System-on-Chip
• Publisher: LAP LAMBERT Academic Publishing
• Publication Date: 2012
• Language: English
• ISBN 10: 3659291889
• ISBN 13: 9783659291883
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 220W x 150H x 10D millimeters 220 millimeters width by 150 millimeters height by 10 millimeters depth
• Weight: 233 grams
• Seller catalogs:
  • Bücher

About this title

Synopsis

Low-dropout regulators (LDRs) are indispensable components widely used in system-on-chip (SoC) designs to power up noise-sensitive blocks. With the proliferation of portable applications, LDRs are required to have accurate and fast regulation with low quiescent current consumption, compact chip area and without requiring any off-chip capacitors. This research focuses on the analysis and design of high-performance CMOS output-capacitor-free LDRs for SoC power management applications. Three different topologies: adaptively biased LDRs, adaptively biased LDRs with subthreshold undershoot-reduction, and LDRs with low-quiescent current and high power-supply-rejections are analyzed, designed and verified. They are powerful candidates for supplying different blocks of SoC: analog, mixed-signal, digital, and RF. Design-oriented and in-depth theoretical analysis is presented. With these topologies at hand, a cost-effective power management solution for SoC is easier-than-ever to construct.

About the Author

Dr. Chenchang Zhan is a Senior Engineer at Qualcomm Technologies Inc., San Diego, CA. He is an expert in the analysis and design of analog, mixed-signal and power management IC's which are the subjects he authored or co-authored many scientific publications. He is the recipient of Best Paper Awards in IEEE ISIC'2009, EDSSC'2010 and ISCAS'2011.