On the Partitioning of Regular Networks Classic Reprint
Language: English
Published by Forgotten Books, 2018
- Softcover
- New

Seller: PBShop.store UK, Fairford, GLOS, United KingdomPBShop.store UK
AbeBooks seller since June 11, 1999
Condition: New
US$ 28.15
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Add to basketItem description from seller
Seller Inventory # LW-9781333311230
- Title
- On the Partitioning of Regular Networks Classic Reprint
- Author
- Marc Snir
- Publisher
- Forgotten Books
- Publication year
- 2018
- Condition
- New
- Binding
- PAP
- Language
- English
- ISBN 10
- 1333311230
- ISBN 13
- 9781333311230
- Item weight
- 123 grams
Learn how regular networks are partitioned under size and perimeter limits, and what that means for real systems.
This technical report examines partitions of regular interconnection networks and how the number of components depends on the connections between them. It connects abstract graph properties to practical questions about data movement in networks such as grids, trees, and shuffle‑exchange graphs. The work also relates partitionability to the ability to support efficient routing, highlighting how networks optimized for routing may partition differently.
Readers will gain a clear view of the relationships between area (component size) and perimeter (external connections), along with concrete bounds and constructions. The discussion covers definitions of partitions, mesh‑connected networks, regular trees, and specific network families, tying theory to architectural constraints in multichip systems and VLSI layouts.
- Definitions of (s, p)-partitions and how they constrain component size and boundary edges.
- Bounds on the maximal component size and minimal partitions in 2D and higher‑dimensional mesh networks.
- Applications to grids, shuffle‑exchange, and related networks, with implications for data motion and routing.
- Connections between partitionability and the efficiency of data permutations and network designs.
Ideal for readers of On the Partitioning of Regular Networks, as well as professionals exploring parallel processing, network design, and VLSI constraints.
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PBShop.store UK
Fairford, GLOS, United Kingdom
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