Planar Double-Gate Transistor : From technology to circuit

Olivier Rozeau

ISBN 10: 9048181089 / ISBN 13: 9789048181087

Published by Springer Netherlands, Springer Netherlands, 2010

About this Item

Druck auf Anfrage Neuware - Printed after ordering - Until the 1990s, the reduction of the minimum feature sizes used to fabricate in- grated circuits, called 'scaling', has highlighted serious advantages as integration density, speed, power consumption, functionality and cost. Direct consequence was the decrease of cost-per-function, so the electronic productivity has largely progressed in this period. Another usually cited trend is the evolution of the in- gration density as expressed by the well-know Moore's Law in 1975: the number of devices per chip doubles every 2 years. This evolution has allowed improving signi cantly the circuit complexity, offering a great computing power in the case of microprocessor, for example. However, since few years, signi cant issues appeared such as the increase of the circuit heating, device complexity, variability and dif culties to improve the integration density. These new trends generate an important growth in development and production costs. Though is it, since 40 years, the evolution of the microelectronics always f- lowed the Moore's law and each dif culty has found a solution.

Seller Inventory # 9789048181087

Bibliographic Details

• Title: Planar Double-Gate Transistor : From technology to circuit
• Publisher: Springer Netherlands, Springer Netherlands
• Publication Date: 2010
• Language: English
• ISBN 10: 9048181089
• ISBN 13: 9789048181087
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 235W x 155H x 13D millimeters 235 millimeters width by 155 millimeters height by 13 millimeters depth
• Weight: 341 grams

About this title

Synopsis

Until the 1990s, the reduction of the minimum feature sizes used to fabricate in- grated circuits, called “scaling”, has highlighted serious advantages as integration density, speed, power consumption, functionality and cost. Direct consequence was the decrease of cost-per-function, so the electronic productivity has largely progressed in this period. Another usually cited trend is the evolution of the in- gration density as expressed by the well-know Moore’s Law in 1975: the number of devices per chip doubles every 2 years. This evolution has allowed improving signi?cantly the circuit complexity, offering a great computing power in the case of microprocessor, for example. However, since few years, signi?cant issues appeared such as the increase of the circuit heating, device complexity, variability and dif?culties to improve the integration density. These new trends generate an important growth in development and production costs. Though is it, since 40 years, the evolution of the microelectronics always f- lowed the Moore’s law and each dif?culty has found a solution.

From the Back Cover

This book on Double-Gates devices and circuit is unique and aims to reinforce the synergy between the research activities on CMOS sub-32nm devices and the design of elementary cells. The goal is to point out how we can take advantage of new transistor structures to come up with new basic cells and concepts that exploit the electrical features of these new devices and the breakthrough they bring.

Planar Double-Gate Transistor will mainly focus on SOI CMOS transistors, fully depleted with double independent planar Gates (Independent Planar Double Gates Transistors: IPDGT), a potential candidate for the sub-32 nm technological nodes as planned by the current ITRS Roadmap.

The book topics are mainly focusing on:

• Detailed description of specific processes that allow the optimization of the CMOS IPDGT device

• CMOS IPDGT modeling, both compact and physical models are presented

• Device characterization

• Design of innovating cells (SRAM cells, basic digital & analog functions) with the objectives to improve the level of integration and the robustness to variability as well as the power consumption optimization, using the degree of freedom introduced by the independent gates.