Priori Wire Length Estimates for Digital Design

Stroobandt, Dirk

ISBN 10: 079237360X / ISBN 13: 9780792373605

Published by Kluwer Academic Publishers, 2001

About this Item

The design of digital (computer) systems requires several design phases. This book aims to develop a priori wire length estimation methods that can help the designer in finding a good lay-out of a circuit in less iterations of physical design steps and that are useful to compare different physical architectures. Num Pages: 298 pages, biography. BIC Classification: TBD; UY. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 235 x 155 x 19. Weight in Grams: 636. . 2001. Hardback. . . . . Books ship from the US and Ireland.

Seller Inventory # V9780792373605

Bibliographic Details

• Title: Priori Wire Length Estimates for Digital Design
• Publisher: Kluwer Academic Publishers
• Publication Date: 2001
• Language: English
• ISBN 10: 079237360X
• ISBN 13: 9780792373605
• Binding: Hardcover
• Condition: New

About this title

Synopsis

The roots of this book, and of the new research field that it defines, lie in the scaling of VLSI technology. With gigahertz system clocks and ever­ accelerating design and process innovations, interconnects have become the limiting factor for both performance and density. This increasing impact of interconnects on the system implementation space necessitates new tools and analytic techniques to support the system designer. With respect to modeling and analysis, the response to interconnect dom­ inance is evolutionary. Atomistic- and grain-level models of interconnect structure, and performance models at multi-gigahertz operating frequencies, together guide the selection of improved materials and process technologies (e. g. , damascene copper wires, low-permittivity dielectrics). Previously in­ significant effects (e. g. , mutual inductance) are added into performance mod­ els, as older approximations (e. g. , lumped-capacitance gate load models) are discarded. However, at the system-level and chip planning level, the necessary response to interconnect dominance is revolutionary. Convergent design flows do not require only distributed RLC line models, repeater awareness, unifi­ cations with extraction and analysis, etc. Rather, issues such as wiring layer assignment, and early prediction of the resource and performance envelope for the system interconnect (in particular, based on statistical models of the system interconnect structure), also become critical. Indeed, system-level interconnect prediction has emerged as the enabler of improved interconnect modeling, more cost-effective system architectures, and more productive design technology.