Processor Array Implementations | Mapping Systems of Affine Recurrence Equations for Digital Signal Processing

Marjan Gusev

ISBN 10: 3659167592 / ISBN 13: 9783659167591

Published by LAP LAMBERT Academic Publishing, 2012

About this Item

Processor Array Implementations | Mapping Systems of Affine Recurrence Equations for Digital Signal Processing | Marjan Gusev | Taschenbuch | 288 S. | Englisch | 2012 | LAP LAMBERT Academic Publishing | EAN 9783659167591 | Verantwortliche Person für die EU: BoD - Books on Demand, In de Tarpen 42, 22848 Norderstedt, info[at]bod[dot]de | Anbieter: preigu.

Seller Inventory # 106342173

Bibliographic Details

• Title: Processor Array Implementations | Mapping Systems of Affine Recurrence Equations for Digital Signal Processing
• Publisher: LAP LAMBERT Academic Publishing
• Publication Date: 2012
• Language: English
• ISBN 10: 3659167592
• ISBN 13: 9783659167591
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 220W x 150H x 18D millimeters 220 millimeters width by 150 millimeters height by 18 millimeters depth
• Weight: 447 grams
• Seller catalogs:
  • Bücher

About this title

Synopsis

Regular processor array implementations lack efficiency due to limitations set by data dependences in order to enable regular data flow. Efficient processor arrays implement data flow of all variables and avoid static variables that require intensive data loads from memory introducing idle processor activity. Most of existing design methods and techniques that map algorithms onto processor arrays are based on linear mappings and just transform the algorithm dependence graphs in space-time graphs. Obtained processor arrays do not reach the required efficiency, producing “bubbles” when the processor is not performing a reasonable operation in alternative time moments, i.e. producing idle activity. The results in this research show implementations that can eliminate mentioned problems and can reach maximum efficiency, except for processor data load and store activities. The implementations are based on non-linear transformations that include folding, double mapping and fast systolic designs. There are theoretical and experimental proofs which designs can reach the most efficient processor array implementations by introducing the fastest processors array implementations

About the Author

He is a professor at the University Sts Cyril and Methodius, Skopje, Macedonia and has published more than 533 publications in Computer Architecture, Parallel Processing, Computer Networks, Internet, and Cloud Computing in related journals and conferences; coordinated 13 EU funded projects, 28 research projects; 3 labs and 2 educational academies