Programmable Reed-Solomon Codec : Design and Implementation

Jaydeb Bhaumik

ISBN 10: 3659457264 / ISBN 13: 9783659457265

Published by LAP LAMBERT Academic Publishing, 2013

About this Item

nach der Bestellung gedruckt Neuware - Printed after ordering - The modern communications systems become faster day by day. Errors almost inevitably occur during the transmission, storage or processing of information, because of noise and interference in communication channels, or imperfections in storage media. Therefore, the detection and correction of errors in information have become very important issue. Reed-Solomon (RS) codes are non-binary, cyclic error correcting codes which are very much effective for the detection and correction of burst errors. RS codes are defined over Galois field. The encoder appends parity symbols to the data using a predetermined algorithm before transmission. Decoder detects and corrects errors. VLSI design creates a flexible and high degree of parallelism for implementing the RS codes. The purpose of this thesis is to design and implement a programmable RS encoder and decoder on an FPGA platform. In this work, a modified architecture for a programmable RS encoder and decoder has been proposed. Employing the proposed scheme, RS codes can be generated and decoded for different generator polynomials. Also an RS (255, 251) encoder and decoder have been implemented on an FPGA platform.

Seller Inventory # 9783659457265

Bibliographic Details

• Title: Programmable Reed-Solomon Codec : Design and Implementation
• Publisher: LAP LAMBERT Academic Publishing
• Publication Date: 2013
• Language: English
• ISBN 10: 3659457264
• ISBN 13: 9783659457265
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 220W x 150H x 5D millimeters 220 millimeters width by 150 millimeters height by 5 millimeters depth
• Weight: 113 grams

About this title

Synopsis

The modern communications systems become faster day by day. Errors almost inevitably occur during the transmission, storage or processing of information, because of noise and interference in communication channels, or imperfections in storage media. Therefore, the detection and correction of errors in information have become very important issue. Reed-Solomon (RS) codes are non-binary, cyclic error correcting codes which are very much effective for the detection and correction of burst errors. RS codes are defined over Galois field. The encoder appends parity symbols to the data using a predetermined algorithm before transmission. Decoder detects and corrects errors. VLSI design creates a flexible and high degree of parallelism for implementing the RS codes. The purpose of this thesis is to design and implement a programmable RS encoder and decoder on an FPGA platform. In this work, a modified architecture for a programmable RS encoder and decoder has been proposed. Employing the proposed scheme, RS codes can be generated and decoded for different generator polynomials. Also an RS (255, 251) encoder and decoder have been implemented on an FPGA platform.

About the Author

Dr.J. Bhaumik is working as an Asoc. Prof. in the Dept. of ECE, HIT. He obtained his PhD degree from IIT Kharagpur. He received his B.Tech & M.Tech from CU. His research areas: VLSI Design & Cryptography.Mr.A.S.Das is working as a JRF at Sidho-Kanho Birsha University. He did his M.Tech in ECE from WBUT. His research areas:ECC,Optical comm & VLSI.