Reconfigurable Processor Array A Bit Sliced Parallel Computer (USA)

Rushton, A.

ISBN 10: 0256074216 / ISBN 13: 9780256074215

Published by Irwin Professional Publishing, 1991

About this Item

Most items will be dispatched the same or the next working day. A copy that has been read but remains in clean condition. All of the pages are intact and the cover is intact and the spine may show signs of wear. The book may have minor markings which are not specifically mentioned. A tan to the pages.

Seller Inventory # wbb0023439025

Bibliographic Details

• Title: Reconfigurable Processor Array A Bit Sliced Parallel Computer (USA)
• Publisher: Irwin Professional Publishing
• Publication Date: 1991
• Language: English
• ISBN 10: 0256074216
• ISBN 13: 9780256074215
• Binding: Soft cover
• Condition: Good
• Weight: 505 grams

About this title

Synopsis

Processor arrays have established themselves as an inexpensive form of parallel computer suitable for a wide range of highly parallel applications. They achieve their performance by huge replication of simple processors known as processing elements or PE. This book investigates enhancements to the conventional bit serial PE with the aim of improving its performance in situations where the small grain parallelism of a single instruction-stream, multiple data stream (SIMD) class parallel computer architecture is inefficient.

The book describes the development of an SIMD class parallel computer based on processor arrays. Surprisingly, for many problems a large array of bit serial processing elements is a better source of processing power than a small array of complex processors, and the reconfigurable processor array described here is enhanced with floating-point, multiplication, and data cache facilities to improve the operation of such arrays. The RPA also has features that allow clusters of processing elements to operate on each data item so that hardware parallelism can be matched with data parallelism.

The implementation of the architecture as a chip design, for possible VLSI realization, is described, and an appendix contains a high level formal description of the processing element in a registertransfer language.

Andrew Rushton teaches at the University of Southampton. Reconfigurable Processor Array is included in the series Research Monographs in Parallel and Distributed Computing, copublished with Pitman Publishing.