Reconfigurable Transform Architecture for Multiple Video Codecs | Implementation of a low cost unified integer DCT architecture for four video codec: AVS, VC-1, H.264/AVC and HEVC

Muhammad Ali Martuza (u. a.)

ISBN 10: 3659480568 / ISBN 13: 9783659480560

Published by LAP LAMBERT Academic Publishing, 2013

About this Item

Reconfigurable Transform Architecture for Multiple Video Codecs | Implementation of a low cost unified integer DCT architecture for four video codec: AVS, VC-1, H.264/AVC and HEVC | Muhammad Ali Martuza (u. a.) | Taschenbuch | 80 S. | Englisch | 2013 | LAP LAMBERT Academic Publishing | EAN 9783659480560 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu.

Seller Inventory # 105599064

Bibliographic Details

• Title: Reconfigurable Transform Architecture for Multiple Video Codecs | Implementation of a low cost unified integer DCT architecture for four video codec: AVS, VC-1, H.264/AVC and HEVC
• Publisher: LAP LAMBERT Academic Publishing
• Publication Date: 2013
• Language: English
• ISBN 10: 3659480568
• ISBN 13: 9783659480560
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 220W x 150H x 6D millimeters 220 millimeters width by 150 millimeters height by 6 millimeters depth
• Weight: 137 grams
• Seller catalogs:
  • Bücher

About this title

Synopsis

This book presents a cost-shared architecture to compute multiple integer discrete cosine transform (Int-DCT) of four video codecs: AVS, VC-1, H.264/AVC and HEVC (under development). Based on the symmetric structure of the matrices and the similarity in matrix operation, we develop a generalized ‘‘decompose and share’’ algorithm to compute both 4x4 and 8x8 Int-DCT. The algorithm is later applied to the video codecs. The hardware share approach ensures maximum circuit reuse during the computation. The architecture is designed with only adders and shifters to reduce the hardware cost significantly. The design is implemented on FPGA and later synthesized in CMOS 0.18um technology. The results show significant reduction in hardware cost and meet the requirements of real time video coding applications.

About the Author

Muhammad A. Martuza pursued his B.Sc. in ETE from North South University, Bangladesh (2009) and M.Sc. in ECE from University of Saskatchewan (2012). He is now conducting research on thin film transistors at University of Waterloo as PhD candidate. His field of interests are nano-scale semiconductor device fabrication and real-time VLSI systems.