Research Infrastructures for Hardware Accelerators. This item is unavailable.Research Infrastructures for Hardware Accelerators

Hardware acceleration in the form of customized datapath and control circuitry tuned to specific applications has gained popularity for its promise to utilize transistors more efficiently. Historically, the computer architecture community has focused on general-purpose processors, and extensive research infrastructure has been developed to support research efforts in this domain. Envisioning future computing systems with a diverse set of general-purpose cores and accelerators, computer architects must add accelerator-related research infrastructures to their toolboxes to explore future heterogeneous systems. This book serves as a primer for the field, as an overview of the vast literature on accelerator architectures and their design flows, and as a resource guidebook for researchers working in related areas.

Yakun Sophia Shao is a Ph.D. candidate in Computer Science at Harvard University, working with Professor David Brooks. Her primary research interests lie in the general area of computer architecture, with a particular focus on modeling and design for heterogeneous architectures. She received her B.S. degree in Electrical Engineering from Zhejiang University, China and her S.M. degree in Computer Science from Harvard University. Her paper was selected as one of the Top Picks in Computer Architecture in 2014. She is a Siebel Scholar and a recipient of the IBM Ph.D. Fellowship.David Brooks is the Haley Family Professor of Computer Science in the School of Engineering and Applied Sciences at Harvard University. He joined Harvard in 2002 after spending one year as a research staff member at IBM T.J. Watson Research Center. Professor Brooks received his B.S. in Electrical Engineering at the University of Southern California and M.A. and Ph.D. degrees in Electrical Engineering at Princeton University. Professor Brooks has received several honors and awards including the ACM Maurice Wilkes Award, NSF CAREER award, IBM Faculty Partnership Award, and DARPA Young Faculty Award. He has received best paper awards at MICRO, HPCA, and ICCD and has had several papers selected for IEEE Micro’s “Top Picks in Computer Architecture� since 2005. His research interests include technology-aware computer design, with an emphasis on power-efficient computer architectures for high-performance and embedded systems.