A Roadmap for Formal Property Verification

Pallab Dasgupta

ISBN 10: 1402047576 / ISBN 13: 9781402047572

Published by Springer Jul 2006, 2006

About this Item

Neuware - Integrating formal property verification (FPV) into an existing design process raises several interesting questions. Have I written enough properties Have I written a consistent set of properties What should I do when the FPV tool runs into capacity issues This book develops the answers to these questions and fits them into a roadmap for formal property verification - a roadmap that shows how to glue FPV technology into the traditional validation flow. A Roadmap for Formal Property Verification explores the key issues in this powerful technology through simple examples - you do not need any background on formal methods to read most parts of this book.

Seller Inventory # 9781402047572

Bibliographic Details

• Title: A Roadmap for Formal Property Verification
• Publisher: Springer Jul 2006
• Publication Date: 2006
• Language: English
• ISBN 10: 1402047576
• ISBN 13: 9781402047572
• Binding: Buch
• Condition: Neu
• Dimensions: 247W x 162H x 17D millimeters 247 millimeters width by 162 millimeters height by 17 millimeters depth
• Weight: 621 grams

About this title

Synopsis

Integrating formal property verification (FPV) into an existing design process raises several interesting questions. Have I written enough properties? Have I written a consistent set of properties? What should I do when the FPV tool runs into capacity issues? This book develops the answers to these questions and fits them into a roadmap for formal property verification – a roadmap that shows how to glue FPV technology into the traditional validation flow. A Roadmap for Formal Property Verification explores the key issues in this powerful technology through simple examples – you do not need any background on formal methods to read most parts of this book.

About the Author

The author leads the Formal Verification Group at the Indian Institute of Technology, Kharagpur (http://www.facweb.iitkgp.ernet.in/~pallab/forverif.html). He has collaborations with leading companies, including Intel, Sun Microsystems, Synopsys, Texas Instruments, National Semiconductors, General Motors, Interra Systems and Virtio Corp, on developing formal methods for design verification. The author is a senior member of IEEE.