A Roadmap for Formal Property Verification

Pallab Dasgupta

ISBN 10: 9048171857 / ISBN 13: 9789048171859

Published by Springer Netherlands, Springer Netherlands Okt 2010, 2010

About this Item

This item is printed on demand - Print on Demand Titel. Neuware -Integrating formal property verification (FPV) into an existing design process raises several interesting questions. Have I written enough properties Have I written a consistent set of properties What should I do when the FPV tool runs into capacity issues This book develops the answers to these questions and fits them into a roadmap for formal property verification ¿ a roadmap that shows how to glue FPV technology into the traditional validation flow. A Roadmap for Formal Property Verification explores the key issues in this powerful technology through simple examples ¿ you do not need any background on formal methods to read most parts of this book.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 268 pp. Englisch.

Seller Inventory # 9789048171859

Bibliographic Details

• Title: A Roadmap for Formal Property Verification
• Publisher: Springer Netherlands, Springer Netherlands Okt 2010
• Publication Date: 2010
• Language: English
• ISBN 10: 9048171857
• ISBN 13: 9789048171859
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 240W x 160H x 15D millimeters 240 millimeters width by 160 millimeters height by 15 millimeters depth
• Weight: 434 grams

About this title

Synopsis

Integrating formal property verification (FPV) into an existing design process raises critical questions: Have I written enough properties? Have I written a consistent set of properties? What should I do when the FPV tool runs into capacity issues? This book develops the answers to these questions and fits them into a roadmap for formal property verification – a roadmap that shows how to glue FPV technology into the traditional validation flow.

About the Author

The author leads the Formal Verification Group at the Indian Institute of Technology, Kharagpur (http://www.facweb.iitkgp.ernet.in/~pallab/forverif.html). He has collaborations with leading companies, including Intel, Sun Microsystems, Synopsys, Texas Instruments, National Semiconductors, General Motors, Interra Systems and Virtio Corp, on developing formal methods for design verification. The author is a senior member of IEEE.