Scalable Multi-Core Architectures: Design Methodologies and Tools

Jantsch, Axel (Editor)

ISBN 10: 144196777X / ISBN 13: 9781441967770

Published by Springer Verlag, 2011

About this Item

223 pages. 8.50x6.25x0.75 inches. In Stock.

Seller Inventory # x-144196777X

Bibliographic Details

• Title: Scalable Multi-Core Architectures: Design Methodologies and Tools
• Publisher: Springer Verlag
• Publication Date: 2011
• Language: English
• ISBN 10: 144196777X
• ISBN 13: 9781441967770
• Binding: Hardcover
• Condition: Brand New

About this title

Synopsis

As Moore’s law continues to unfold, two important trends have recently emerged. First, the growth of chip capacity is translated into a corresponding increase of number of cores. Second, the parallelization of the computation and 3D integration technologies lead to distributed memory architectures. This book describes recent research that addresses urgent challenges in many-core architectures and application mapping. It addresses the architectural design of many core chips, memory and data management, power management, design and programming methodologies. It also describes how new techniques have been applied in various industrial case studies.

From the Back Cover

As Moore’s law continues to unfold, two important trends have recently emerged. First, the growth of chip capacity is translated into a corresponding increase of number of cores. Second, the parallalization of the computation and 3D integration technologies lead to distributed memory architectures.

This book provides a current snapshot of industrial and academic research, conducted as part of the European FP7 MOSART project, addressing urgent challenges in many-core architectures and application mapping. It addresses the architectural design of many core chips, memory and data management, power management, design and programming methodologies. It also describes how new techniques have been applied in various industrial case studies.

• Describes trends towards distributed memory architectures and distributed power management;
• Integrates Network on Chip with distributed, shared memory architectures;
• Demonstrates novel design methodologies and frameworks for multi-core design space exploration;
• Shows how midlleware services (dynamic data management) can be integrated into and support by the platform.