Single Port Memory Design Using VHDL: Synthesis and Simulation

Bhasin, Samridhi

ISBN 10: 3846590606 / ISBN 13: 9783846590607

Published by LAP LAMBERT Academic Publishing, 2014

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Bibliographic Details

• Title: Single Port Memory Design Using VHDL: Synthesis and Simulation
• Publisher: LAP LAMBERT Academic Publishing
• Publication Date: 2014
• Language: English
• ISBN 10: 3846590606
• ISBN 13: 9783846590607
• Binding: paperback
• Condition: New
• Book Type: book

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Synopsis

In today’s fast paced technology race there are many aspects of a computer that can be improved upon. Memory is an integral part of how a computer works and involves many different complex levels of hierarchy. Semiconductor memory is an electronic data storage device often used as computer memory, implemented on semiconductor-basis integrated circuits. It is made in many different types and technologies. A simple yet efficient method is presented to explore the design space for memory synthesis which deals with single-port memory synthesis according to the design constraints. The application of this method to different synthesis examples is illustrated and demonstrated. With suitable modifications, the technique could be applied to multiport memory synthesis in which the maximum number of read ports is different from the maximum number of write ports. Memory is designed in VHDL to produce the RTL schematic of the desired circuit. After that, the generated schematic can be verified using simulation software which shows the waveforms of inputs and outputs of the circuit after generating the appropriate testbench. All the chapters start with a brief explanation of design stage.

About the Author

Samridhi Bhasin graduated from Delhi University,Hansraj College with Bachelor of Science(Hons)in Electronics in 2012.She is pursuing M.Sc.Electronics from Banasthali Vidyapith,Banasthali,doing training in BARC,Mumbai.She coordinated workshops in field of ImageProcessing & worked in academic projects.Her research interests are VLSI,Embedded systems.